mannraval1's starred repositories

awesome-semiconductor-startups

List of awesome semiconductor startups

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FPGA-ASIC-Roadmap

A roadmap for those who want to build a career as an FPGA / ASIC Engineer

License:CC-BY-SA-4.0Stargazers:157Issues:0Issues:0
Language:VerilogStargazers:3Issues:0Issues:0
Language:SystemVerilogStargazers:35Issues:0Issues:0

Machine-Learning-Models

Decision Trees, Random Forest, Dynamic Time Warping, Naive Bayes, KNN, Linear Regression, Logistic Regression, Mixture Of Gaussian, Neural Network, PCA, SVD, Gaussian Naive Bayes, Fitting Data to Gaussian, K-Means

Language:MatlabStargazers:325Issues:0Issues:0

MATLAB-MAL114

MAL114 - Linear Algebra MATLAB Codes: QR decomposition and eigenvalues, Gauss-Jacobi, Gauss-Jordan, Gauss-Seidel, Graham-Schmidt, Jacobi Eigenvalues, Projection, Successive over Relaxation, System of Equations.

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PatchMatch-Matlab

PatchMatch Stereo in Matlab

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Stereo-Vision-to-estimate-depth-in-an-image

ENPM673: Project 3. Implementing a stereo vision pipeline to find the depth of an image. This project will generate a heat map indicating depth which has been calculated using disparity between correspondences

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Fast-Stereo-Disparity-Estimator

MATLAB implementation of fast stereo disparity estimator.

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Depth-Estimation-using-Stereovision

In this project, we try to implement the concept of Stereo Vision. We test the code on 3 different datasets, each of them contains 2 images of the same scenario but taken from two different camera angles. By comparing the information about a scene from 2 vantage points, we can obtain the 3D information by examining the relative positions of objects.

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MIPS-5-stage-pipelined-control-and-datapath

Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding control, hazard detection and stalling units are also implemented to improve the efficiency of the pipeline. The designed processor can be tested by initializing the instruction memory with test instructions and obtaining the corresponding register contents by generating waveforms on ModelSim.

Language:VerilogLicense:MITStargazers:2Issues:0Issues:0

QCM

Quantum Circuit Modelling Using State Vector and Heisenberg Representations

Language:SystemVerilogLicense:BSD-3-ClauseStargazers:9Issues:0Issues:0

Image-Warping

Creating image panoramas by image warping and image stitching

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Image_Stiching

Image Stiching for Panoramic Images

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Image-Stitching-OpenCV

Simple image stitching algorithm based on SIFT, homography, KNN and Ransac in Python and OpenCV

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HDL-Bits-Solutions

This is a repository containing solutions to the problem statements given in HDL Bits website.

Language:VerilogLicense:UnlicenseStargazers:300Issues:0Issues:0

FBMC

Compares FBMC to OFDM based schemes. Reproduces all figures from “Filter bank multicarrier modulation schemes for future mobile communications”, IEEE Journal on Selected Areas in Communications, 2017.

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Vein-Detection-System

System for detecting vein patterns.

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RISC-Pipelined-Processor-32-bit-Verilog

Simple Pipelined 32 bit RISC Processor

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FPGA-Verilog

Practices related to the fundamental level of the programming language Verilog.

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SPI

Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI bus provides a synchronized serial link with performance in MHz range.The project implements the bridge between the two protocols and serves as an interface between these two which allow direct communication and a solution to reduce development time and cost for complex embedded systems.

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DA-Based-LMS-Adaptive-filter

Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be effectively used to implement FIR, IIR and FFT type.The DA logic replaces the MAC operation of convolution summation o into a bit-serial look-up table read and addition operation .

Language:VerilogStargazers:14Issues:0Issues:0

viterbi_decoder

Hardware Viterbi Decoder in verilog

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verilog-starter-tutorials

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

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camera_image_warping_exp

camera image warping experiment code: to find the correct transform between OpenCV image stitching and standard zyx camera perspective warping.

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image_transformation

Perform image transformations like Euclidean, Similarity, Affine, Perspective and 2-D transformations

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perspective-transform

A perspective transform application that plays with different homography principles to change the perspective of an image.

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PerspectiveTransform

A python script to get Perspective Transformed(birds eye view) version of an input image using OpenCV. This is analogous to the CamScanner select region feature.

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