mahmedadawy2013

mahmedadawy2013's repositories

UVM_Counter

Language:SystemVerilog1 10

UVM_UART

Language:SystemVerilog1 10

-Design_Simple-Up-Down-Counter-

Language:Verilog010

CoCotb_AES128_Encryption

Language:SystemVerilog010

CoCotb_ALU

Language:Python010

CoCotb_Counter

Language:Python000

Cocotb_Project

Language:SystemVerilog010

CoCotb_Register_Memory

Language:Python010

Design_Door_Controller

Language:Verilog010

Design_MIPS

Language:Verilog010

Design_Simple_Arithmetic_Logic_Unit-

Language:Verilog000

Design_UART_TX_RX

Language:Verilog000

explore-with-postman

Various materials for Exploratory API Testing with Postman workshops

MIT000

Get-Mango

Simple 2D Platformer Game

Language:C#000

MRMOSFET

010

PyUVM_CLK_Generator

Language:Python010

PyUVM_I2C_Memory

Language:Python000

PyUVM_Project

Language:SystemVerilog000

PyUVM_SPI-Memory

Language:Python010

register_mem

010

STUDENT-INFO-

Language:C010

SV_Counter

Language:SystemVerilog000

SV_TB_Register_Memory

Language:SystemVerilog000

SV_UVM_Concept_Project

Language:JavaScript000

TRIAL

Try carval

Language:VerilogApache-2.0010

UVM_LFSR

Language:SystemVerilog010

UVM_Register_Memory

Language:SystemVerilog010