mahdiolfat

Mahdi Olfat's repositories

All things EAGLE CAD

MIPS processor with a 5-stage pipeline

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Statistical Digital Signal Processing Algorithms

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Snoops in the internet based on information in an excel mailing list.

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Synthesizable Kirsch Edge Detector for 90nm CMOS; 4-stage fully pipelined design; 205MHz (4.9ns);

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My C implementations of interesting code snippets.

GPL-3.0000

Statistical Digital Signal Processing and Modeling

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