magicYang1573

tsne-cuda

GPU Accelerated t-SNE for CUDA with Python bindings

SurviveNWPU-CSManual

A Manual on Surviving in CS of NWPU

GenshinCPU

Our repository for NSCSCC

llm-hardware-test-generation

chipgptft

llm-hardware-test-generation

MasterRTL

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

HeadSpace

An DSP library written in Python for performing HRTFs

MachineLearning

Basic Machine Learning and Deep Learning

PointPWC

PointPWC-Net is a deep coarse-to-fine network designed for 3D scene flow estimation from 3D point clouds.

ContourNet

A PyTorch implementation of "ContourNet: Taking a Further Step toward Accurate Arbitrary-shaped Scene Text Detection" (CVPR2020)

LPV

The official code of Linguistic More: Taking a Further Step toward Efficient and Accurate Scene Text Recognition (IJCAI2023)

MOSTEL

Video-LLaMA

Video-LLaMA: An Instruction-tuned Audio-Visual Language Model for Video Understanding

EVFlowNet-pytorch

EVFlowNet in pytorch

simulator-independent-coverage

Project Repo for the Simulator Independent Coverage Research

ChampSim

ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.

Tarsel

verilator

Verilator open-source SystemVerilog simulator and lint system

rtl-fuzz-lab

A Modular Open-Source Hardware Fuzzing Framework

constellation

A Chisel RTL generator for network-on-chip interconnects

ChiselFV

A Formal Verification Framework for Chisel

chisel-template

A template project for beginning new Chisel work

chisel

Chisel: A Modern Hardware Design Language

chiseltest

The batteries-included testing and formal verification library for Chisel-based RTL designs.

chiselverify

A dynamic verification library for Chisel.

pillars

An integrated CGRA design framework

purlin

A versatile toolkit for programmable on-chip network generation and simulation

hw-fuzzing

AFL

american fuzzy lop - a security-oriented fuzzer