Zexun Luo (lzxqaq)

lzxqaq

Geek Repo

Location:Shenzhen, China

Home Page:https://lzxqaq.com

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Zexun Luo's starred repositories

Language:RustLicense:Apache-2.0Stargazers:11Issues:0Issues:0

piano

🎹Play the piano with the keyboard - 用键盘8个键演奏一首蒲公英的约定送给自己或月亮代表我的心送给她

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EDA_FeatureColle

A collection of license features from a varity of EDA vendors

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ModernCppStarter

🚀 Kick-start your C++! A template for modern C++ projects using CMake, CI, code coverage, clang-format, reproducible dependency management and much more.

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fixSegfaultVCS

There is segmentation fault of VCS which should be fixed.

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Formal-Verification-With-VC-Formal--Tutorials-and-Examples

This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our goal is to help both beginners and experienced users understand the principles of formal verification and how to apply them effectively using VC Formal.

License:GPL-3.0Stargazers:4Issues:0Issues:0

awesome-web3-formal-verification

A curated list of awesome web3 formal verification resources -- including tools, tutorials, articles and more.

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rocket-chip

Rocket Chip Generator

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core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

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chisel-interface

The 'missing header' for Chisel

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tclap

Templatized C++ Command Line Parser mirror

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tech_char

90nm, 65nm, 32nm synthesis

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ASIC-Design-Roadmap

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

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pdfsam

PDFsam, a desktop application to split, merge, mix, rotate PDF files and extract pages

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templates

Document templates for open-source projects (README, CONTRIBUTING, GitHub templates)

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chat

chat web app for teams, sass with user management and ratelimit, support chatgpt(openai & azure), claude, gemini and ollama model

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CVC4-archived

CVC4 is an efficient open-source automatic theorem prover for satisfiability modulo theories (SMT) problems.

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bitwuzla

Bitwuzla is a Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, floating-point arithmetic, arrays and uninterpreted functions and their combinations. Its name is derived from an Austrian dialect expression that can be translated as “someone who tinkers with bits”.

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json

JSON for Modern C++

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geany

A fast and lightweight IDE

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svlint

SystemVerilog linter

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sv-parser

SystemVerilog parser library fully compliant with IEEE 1800-2017

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chhRobotics_CPP

自动驾驶规划控制常用算法c++代码实现

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rust-by-practice

Learning Rust By Practice, narrowing the gap between beginner and skilled-dev through challenging examples, exercises and projects.

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SystemVerilogCourse

This is a detailed SystemVerilog course

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markdown-resume

:necktie:支持 Markdown 和富文本的在线简历排版工具

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lorina

C++ parsing library for simple formats used in logic synthesis and formal verification

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keccak-asic

"Design of ASIC" - appointment project

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Markdown-Resume

⭐️ Markdown 简历模版

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