lvcargnini

fpu

synthesiseable ieee 754 floating point library in verilog

systemverilog_language_plugin

agnoster-zsh-theme

A ZSH theme designed to disclose information contextually, with a powerline aesthetic

ariane

Ariane is a 6-stage RISC-V CPU

atom

:atom: The hackable text editor

Blaster

CryptRaider

Learnign to code for Unreal 5

embench-iot

The main Embench repository

fpnew

[UNRELEASED] Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

grift

Galois RISC-V ISA Formal Tools

growl

The ultimate Notiication System for OS X

klayout

KLayout Main Sources

linux-pine64

Linux Kernel for Pine64 Board

llvm

Mirror of official llvm git repository located at http://llvm.org/git/llvm. Updated every five minutes.

llvm-project

This is the canonical git mirror of the LLVM subversion repository. Please see http://llvm.org/ for instructions on contributing to LLVM.

mesim

Memory Simulator

omnixtend-1

OmniXtend cache coherence protocol

OpenSTA

OpenSTA engine

powerline

Powerline is a statusline plugin for vim, and provides statuslines and prompts for several other applications, including zsh, bash, tmux, IPython, Awesome and Qtile.

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

riscv-tools

RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)

rv8

RISC-V simulator for x86-64

rv_plic

Implementation of a RISC-V-compatible Platform Interrupt Controller (PLIC)

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

SuperScalar-RISCV-CPU

super-scalar out-of-order rv32imc cpu core, 4.2/2.3 DMIPS/MHz, 2/3-stage

swerv_eh1

A directory of Western Digital’s RISC-V SweRV Cores

tensorflow

An Open Source Machine Learning Framework for Everyone

testingGHEDA

Testing GitHub automation on EDA

ToonTanks

Project used to learn Unreal Engine with C++

WarehouseWreckage

Learnign to use Asseets and Player Control on Unreal 5