lsplf's repositories
AISP_NR
2D AI-NR model for raw images, including dataset、training、infer.
axi_vip_master
Sample UVM code for axi ram dut
CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
complexPyTorch
A high-level toolbox for using complex valued neural networks in PyTorch
Coursera-ML-AndrewNg-Notes
吴恩达老师的机器学习课程个人笔记
deep-learning-v2-pytorch
Projects and exercises for the latest Deep Learning ND program https://www.udacity.com/course/deep-learning-nanodegree--nd101
deeplearning_ai_books
deeplearning.ai（吴恩达老师的深度学习课程笔记及资源）
dipy
DIPY is the paragon 3D/4D+ imaging library in Python. Contains generic methods for spatial normalization, signal processing, machine learning, statistical analysis and visualization of medical images. Additionally, it contains specialized methods for computational anatomy including diffusion, perfusion and structural imaging.
ez_ISP
This is a easy ISP (ez_ISP) for RAW to RGB conversion.
FiberODF
Compute Fiber Orientation Distribution from Volumetric Images Based on Fourier Decomposition
hamming_ecc
[Verilog+Python] python script automatic generated hamming ECC verilog code
hdlgadgets
human-in-the-loop HDL training tool
HDR-ISP
An ISP Pipeline For HDR CMOS Image Sensor
infinite-isp
A camera isp (image signal processor) pipeline that contains modules with simple to complex algorithms implemented at the application level.
ISP-pipeline-hdrplus
image-processing(图形处理),camera, isp ,HDRplus
leetcode
LeetCode Solutions: A Record of My Problem Solving Journey.( leetcode题解，记录自己的leetcode解题之路。)
make_tutorial
this is about makefile tutorial
openISP
Image Signal Processor
python_script_for_register_module
python script to generate register component in UVM
round-robin_arbiter
[Verilog] round-robin arbiter which support parameterized configuration request number
simple-camera-pipeline
A simple and light-weight camera image processing pipeline
skid_buffer
Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
STM32_HOST_UVC_Camera
Example of connecting USB Web camera to STM32F4 USB HOST
Vitis_Libraries
Vitis Libraries
zynq-video-board
Open Hardware carrier board supporting modules with Zynq 7000 All Programmable SoC devices.