lomano77's starred repositories
Verilog-Design-Examples
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier
riscv-iommu
IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
tls-cryptography
TLS 구현으로 배우는 암호학 [C++로 만드는 HTTPS 서비스]
DPI_Tutorial
SystemVerilog Direct Programming Interface (DPI) Tutorial
RTL-Design-For-FPGA
Engineering Program on RTL Design for FPGA Accelerator
network_vpi_lib
Network VPI Library is a collection of VPI (Verilog Programming Interface) tasks that handles network packets, which include Ethernet, IP, UDP, TCP and PTPv2.
AMBA_AXI_AHB_APB
AMBA bus lecture material
RACE_protocol
RACE Protocol: Remote Access Cache Coherency Enforcement Protocol
DLR_Projects
Deep learning projects using DLR (Deep Learning Routines)
HiPi-Bus_shared_bus_protocol
The HiPi+Bus (하이파이플러스버스) is a shared bus with pipelined protocol supporting multi-cache coherency.
gen_amba_2021
AMBA bus generator including AXI4, AXI3, AHB, and APB
cosim_bfm_library
HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
Deep_Learning_Blocks
DLB (Deep Learning Blocks) as a part of DPU (Deep Learning Processing Unit) is a collection of synthesizable Verilog modules for deep learning inference network.
baremetal-arm
An ebook about bare-metal programming for ARM