[SV] SVExtractTestCode not Extracting Assert Properties

[Schuyler Eldridge]

The following code example results in an unextracted assertion:

hw.module @Foo(in %a : i1, in %b : i1) {
  %true = hw.constant true
  %0 = comb.xor bin %b, %true : i1
  %1 = ltl.delay %true, 1, 0 : i1
  %2 = ltl.concat %a, %1 : i1, !ltl.sequence
  %3 = ltl.implication %2, %0 : !ltl.sequence, i1
  verif.assert %3 label "foo" : !ltl.property
  hw.output
}

This produces with circt-opt -sv-extract-test-code:

hw.module @Foo(in %a : i1, in %b : i1) {
  %true = hw.constant true
  %0 = comb.xor bin %b, %true : i1
  %1 = ltl.delay %true, 1, 0 : i1
  %2 = ltl.concat %a, %1 : i1, !ltl.sequence
  %3 = ltl.implication %2, %0 : !ltl.sequence, i1
  verif.assert %3 label "foo" : !ltl.property
  hw.output
}