liusw-v's repositories
axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
CHARM
CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture (Full Paper accepted to FPGA2023!)
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
gemm_hls
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.
LC-3
An implementation of the LC-3 architecture in VHDL, as described in the book "Introduction to Computing Systems by P&P".
PyTorch-Pretrained-ViT
Vision Transformer (ViT) in PyTorch
SkrSkr
The second place winner for DAC-SDC 2020
trans-fat
An FPGA Accelerator for Transformer Inference
transformer_core
a student trainning project for HLS and transformer
ViTCoD
[HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design
zipcpu
A small, light weight, RISC CPU soft core