Daniel Arevalos's repositories
uart_get_32bit_word
Get an 32 bit word for a determined 32 bit adress
cpu_usm_v1
Educative RISC-V CPU
usm_microcontroller_v1
Undergraduate level RISC-V microcontroller
Cores-SweRV
SweRV EH1 core
Daniel_iic-osic-tools
IIC-OSIC-TOOLS is an all-in-one Docker container for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
digilent-xdc
A collection of Master XDC files for Digilent FPGA and Zynq boards.
OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
cace
Circuit Automatic Characterization Engine
IHP-Open-DesignLib
Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/
IHP-Open-PDK
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
Prueba_CampamentoVLSI
Verilog Demo
serial_debbuger
Serial debugger for RISC-V educational CPU
Symbolic-modified-nodal-analysis
an ipython notebook for symbolic circuit analysis
tt03p5-Wall-Clock-and-Alarm
Submission template for Tiny Tapeout 03p5