Leon Woestenberg's repositories
vivado-docker
Dockerfile to build a Docker image, which can run Vivado from a Docker container.
BlackwireOverview
Blackwire overview, status, roadmap and top-level documentation.
SpinalCorundum
SpinalHDL components for Corundum Ethernet
10g-low-latency-ethernet
10G Low Latency Ethernet
atomic_queue
C++ lockless queue.
BBQ-2
A Block-based Bounded Queue for Exchanging Data and Profiling implemented in C++.
BlackwireSpinal
Blackwire SpinalHDL components implementing WireGuard primitives
ChaCha20Poly1305
ChaCha20-Poly1305 AEAD in VHDL
compiler-explorer-vscode-example
Example of Godbolt-alike C/C++ Compiler Explorer extension like in VSCode
dpdk-stable
Fork of https://github.com/missinglinkelectronics/dpdk-stable, which is a not regularly updated clone of http://git.dpdk.org/dpdk-stable/ with the purpose to develop a new driver for corundum/mqnic (https://github.com/corundum/corundum).
Finka
Finka is the VexRiscv based SoC in Blackwire responsible for WireGuard session management
libvsync
Verification and optimization tool for concurrent code
likewise
Config files for my GitHub profile.
low-latency-ethernet
RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.
Media-Transport-Library
A real-time media transport (LibOS UDP and SMPTE ST 2110) stack based on DPDK and COTS hardware.
MoldUPD64
RTL implementation of a MoldUPD 64 receiver.
NaCl-RISC-V
In this project the NaCl cryptographic library is being ported to RISC-V
Nasdaq-HFT-FPGA
RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.
ndk-core
Common CORE of Network Development Kit (NDK)
ndk-sw
Linux driver and SW tools for Network Development Kit (NDK)
proteus
The SpinalHDL design of the Proteus core, an extensible RISC-V core.
scalable-pipelined-lookup-fpga
Fixed-latency dual-parallel lookup table (CAM-like) mostly for AllowedIP lookups in RX/TX path
stabilizer
Firmware and software for the Sinara Stabilizer module with high speed, low latency ADC/DAC data processing and powerful DSP algorithms in between
UH-JLS
FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器,用来进行无损图像压缩。
vexriscv_ip_repo
Vivado IP repository files for the VexRiscv. If you really still want to use Block Designer...