An Intel FPGA AI NIC implementation that offloads All-Reduce in distributed training
Where to go for documentation?
- PDF: main documentation file.
An Intel FPGA AI NIC implementation that offloads All-Reduce in distributed training
An Intel FPGA AI NIC implementation that offloads All-Reduce in distributed training
Where to go for documentation?
An Intel FPGA AI NIC implementation that offloads All-Reduce in distributed training
BSD 3-Clause "New" or "Revised" License