liangkangnan

tinyriscv

A very simple and easy to understand RISC-V core.

nanoDAP

由于部分淘宝卖家“借鉴”缪斯实验室出的nanoDAP详情及描述，请大家认准Muse Lab官方店铺

riscv

RISC-V CPU Core (RV32IM)

nodemcu-firmware

Lua based interactive firmware for ESP8266, ESP8285 and ESP32

riscv-openocd

Fork of OpenOCD that has RISC-V microcontroller support

btstack

Dual-mode Bluetooth stack, with small memory footprint.

CMSIS-DAP

STM32 port for CMSIS-DAP with additional serial (CDC) support

CMSIS_5

CMSIS Version 5 Development Repository

core_spiflash

SPI-Flash XIP Interface (Verilog)

e200_opensource

The Ultra-Low Power RISC Core

exactstep

Instruction accurate instruction set simulator for RISC-V and ARM-v6m

freedom

Source files for SiFive's Freedom platforms

gnu-mcu-eclipse-build-tools-2.11-20180428-1604-win64

gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.2-20190521-0004-win64

JMCUProg

MCU programmer using J-LINK Debugger, using Keil MDK's *.FLM Flashing Algorithm

liangkangnan.github.io

mingw-std-threads

Standard threads implementation currently still missing on MinGW GCC on Windows

openocd_riscv

Spen's Official OpenOCD Mirror

OpenOCDonMinGW

OpenOCD binary builder on MSYS2/MinGW

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

riscv-dbg

RISC-V Debug Support for our PULP Cores

riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

rocc-software

C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

rocket-rocc-examples

Tests for example Rocket Custom Coprocessors

sigslot

STM32F103C8T6_CMSIS-DAP_SWO

CMSIS-DAP SWO CDC STM32F103C8T6 BluePill STLINK ARM Debugger

toolchain-verilator

:seedling: Verilator pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation