lfengad / heterosim-1

HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design space exploration is enabled by a wide range of system configurations. A complete simulation flow with compiler support is provided so that a full system simulation can be performed with various performance metrics returned.

Geek Repo

Github PK Tool

This repository is not active

About

Languages

Language:Verilog 38.3%Language:C++ 32.3%Language:C 11.6%Language:Makefile 6.2%Language:VHDL 4.1%Language:HTML 1.8%Language:Assembly 1.0%Language:Roff 0.8%Language:Shell 0.7%Language:Perl 0.6%Language:Tcl 0.6%Language:Objective-C 0.4%Language:Stata 0.4%Language:Python 0.2%Language:Coq 0.2%Language:OCaml 0.2%Language:M4 0.2%Language:CMake 0.1%Language:C# 0.1%Language:Yacc 0.1%Language:TeX 0.1%Language:SystemVerilog 0.0%Language:Lex 0.0%Language:CSS 0.0%Language:Ruby 0.0%Language:XSLT 0.0%Language:Vim Script 0.0%Language:MATLAB 0.0%Language:Emacs Lisp 0.0%Language:Gnuplot 0.0%Language:Ada 0.0%Language:Batchfile 0.0%Language:Fortran 0.0%Language:Mathematica 0.0%Language:Objective-C++ 0.0%Language:QMake 0.0%Language:GDB 0.0%