leoechevarria

hdl-modules

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

underserved

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

uvm_axi

uvm AXI BFM(bus functional model)

UVM_AXI4-Stream

betelbot

Betelgeuse Supernova Twitter Bot

SVA-AXI4-FVIP

YosysHQ SVA AXI Properties

libsv

An open source, parameterized SystemVerilog digital hardware IP library

pin-uart

FPGA board-level debugging and reverse-engineering tool

svlint

SystemVerilog linter

svunit

CIAA_ACC

Here you will find documentation, demos and basic support for this board, developed by INTI - CMNB and Emtech as part of the CIAA project.

corundum

Open source FPGA-based NIC and platform for in-network compute

modern-cpp-tutorial

📚 Modern C++ Tutorial: C++11/14/17/20 On the Fly | https://changkun.de/modern-cpp/