leoechevarria

chisel-tutorial

chisel tutorial exercises and answers

dsp

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

leoechevarria.github.io

RALBot-header

:beetle:Generate C/Verilog header file from compiled SystemRDL input

readme-chess

♟️ Play Multiplayer Chess in a README file!

verilog-axis

Verilog AXI stream components for FPGA implementation