leoZhaoHong

Embedded-Design-Tutorials

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

verilog-ethernet

Verilog Ethernet components for FPGA implementation

zipcpu

A small, light weight, RISC CPU soft core

awesome-digital-ic

A collection of great digital IC project/tutorial/website etc..

LEGv8

A simple implementation about LEGv8 instruction set using Verilog HDL.

verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential

nvguideline_cn

新维加斯中文Mod指南

run

润学全球官方指定GITHUB，整理润学宗旨、纲领、理论和各类润之实例；解决为什么润，润去哪里，怎么润三大问题； 并成为新**人的核心宗教，核心信念。

IWantToRun

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

pp4fpgas-cn

中文版 Parallel Programming for FPGAs

FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

books

【编程随想】收藏的电子书清单（多个学科，含下载链接）

opensource

【编程随想】收藏的开源项目清单

cores

Various HDL (Verilog) IP Cores

basic_verilog

Must-have verilog systemverilog modules

CS106L-201920

julia-mit

Tutorials and information on the Julia language for MIT numerical-computation courses.