leelix2020's starred repositories
MIPS-Processor
5-stage pipelined 32-bit MIPS microprocessor in Verilog
verilog-uart
Verilog UART
sdram-controller
Verilog SDRAM memory controller
5-stage pipelined 32-bit MIPS microprocessor in Verilog
Verilog UART
Verilog SDRAM memory controller