lazyparser / riscv-code-speed-optimization

RISC-V Code Speed Optimization SIG

This is the home of the RISC-V Code Speed Optimization SIG. At present this has the status of a proposed SIG, with a candidate chair and co-chair, and a charter in review.

The SIG is developing a list of candidate projects to pursue. All are invited to submit pull requests to extend the list of candidate projects.

• Candidate Chair: Jeremy Bennett

• Candidate Co-Chair: Wei Wu