lapd-soc's repositories
UARTsv
SystemVerilog UART
Language:SystemVerilog000
UDI_example
example project using UDI interface
GPL-3.0000
ECE571_PDP8_Simulator
PDP8 Simulator Written in SystemVerilog
Language:VHDL000
ECE510-EFV
Coursework for Emerging Function Verification
000
myCPU
My own implementation of a reduced MIPS ISA processor on SystemVerilog
000