lansen0815's repositories
PROFINET-IO-communication-between-3-PLC-s-SIEMENS-S7-1200
PROFINET IO Communication between 3 PLC's SIEMENS S7-1200 using TCP/IP and RT traffic.
automatic-verilog
automatic-verilog-vimscript
CAN-Bus-Controller
An CAN bus Controller implemented in Verilog
CAN_module
CAN Verilog HDL module implementation
CANopen-STM32F1
基于CANfestival的CANopen协议在STM32F1系列单片机上的实现
DSLogic-fw
An open source firmware design for DSLogic
DSLogic-fw-keil
Initial version of DSLogic-fw based on keil
DSLogic-hdl
An open source FPGA design for DSLogic
OpENer
OpENer is an EtherNet/IP stack for I/O adapter devices. It supports multiple I/O and explicit connections and includes objects and services for making EtherNet/IP-compliant products as defined in the ODVA specification.
openPOWERLINK_V2
Release 2 of the openPOWERLINK protocol stack
pcie-sata-adaptor-board
PCB to breakout 8-lane PCI Express to SATA connectors, for use with FPGAs
profinet
Minimal Profinet implementation in Python
rfid-verilog
RFID tag and tester in Verilog
vdent
Verilog Indenter. Simple indent program for Verilog source code. Trims end of line white space and indents lines based on nested depth of code blocks.
verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential.
verilog-arbiter
A look ahead, round-robing parametrized arbiter written in Verilog.
Verilog-Automatic
Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3
veriloggen
Veriloggen: A library for constructing a Verilog HDL source code in Python