lamdo317

ghdl

VHDL 2008/93/87 simulator

open-logic

Open Logic HDL Standard Library

wavedrom.github.io

Digital timing diagram editor

wavedrom

:ocean: Digital timing diagram rendering engine

Microsoft-Activation-Scripts

A Windows and Office activator using HWID / Ohook / KMS38 / Online KMS activation methods, with a focus on open-source code and fewer antivirus detections.

excalidraw

Virtual whiteboard for sketching hand-drawn like diagrams

wotaku

An otaku index for everything!

Main_MiSTer

Main MiSTer binary and Wiki

ip-cores

A huge collection of VHDL/Verilog open-source IP cores scraped from the web

fpga_cores

awesome-cuda-and-hpc

🔥🔥🔥 A collection of some awesome public CUDA, cuBLAS, TensorRT and High Performance Computing (HPC) projects.

awesome

A curated list of awesome resources for HDL design and verification

awesome-hdl

A curated list of awesome HDL, libraries, typical implementation and references.

verilog-axi

Verilog AXI components for FPGA implementation

open-nic

AMD OpenNIC Project Overview

extensions-generic

Netsky's fork of the official Paperback sources.

netskys-extensions

Netsky's sources for Paperback!

30-Days-Of-Python

30 days of Python programming challenge is a step-by-step guide to learn the Python programming language in 30 days. This challenge may take more than100 days, follow your own pace. These videos may help too: https://www.youtube.com/channel/UC7PNRuno1rzYPb1xLa4yktw

eth10g

10Gb Ethernet Switch

linux-insides

A little bit about a linux kernel

no2e1

Nitro E1 FPGA core

verilog-axis

Verilog AXI stream components for FPGA implementation

verilog-ethernet

Verilog Ethernet components for FPGA implementation

corundum

Open source FPGA-based NIC and platform for in-network compute

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

netfpga

NetFPGA 1G infrastructure and gateware

verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential

awesome-hdl

Hardware Description Languages

basic_verilog

Must-have verilog systemverilog modules

cores

Various HDL (Verilog) IP Cores