kkangle / RISCV-VCU118

A synthesizable version of RISCV on VCU118

RISCV-VCU118

A synthesizable version of RISCV on VCU118

This vivado project is built from Sifive/Freedom repo.

The original implementation could be confusing if you want to synthesize and run riscv on your own in vivado, so this repo is created with already generated files using vivado 2016.4.

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A synthesizable version of RISCV on VCU118

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Language:VHDL 61.8%Language:Verilog 35.8%Language:SystemVerilog 2.2%Language:Shell 0.1%Language:Stata 0.0%Language:Tcl 0.0%Language:JavaScript 0.0%Language:Forth 0.0%Language:Coq 0.0%Language:Batchfile 0.0%Language:Pascal 0.0%