kim-sunghoon

Study-materials

bismo

BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing

convNet.pytorch

ConvNet training using pytorch

online-cv

Sunghoon's resume (CV)

py-dev-helper

DiracDeltaNet

PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs

dotfiles

💻⚒️⚒️ Curated Linux dotfiles selection

DSCodeReview

EECV2018-AMC-Training

[ECCV 2018] AMC: AutoML for Model Compression and Acceleration on Mobile Devices.

FPGA-Design-Flow-using-Vivado

This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite

haq

[CVPR 2019, Oral] HAQ: Hardware-Aware Automated Quantization with Mixed Precision.

heterocl

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing

High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS

This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.

HLS-Open-Source-IPs

HLS_designs

Systolic array implementations for Cholesky, LU, and QR decomposition

jetson-gpio

A Python library that enables the use of Jetson's GPIOs

netadapt

This repo contains the official Pytorch reimplementation of the paper "NetAdapt: Platform-Aware Neural Network Adaptation for Mobile Applications".

Neural-Architecture-Search-for-Resource-Constrained-Hardware

practices-of-the-python-pro-template

Project_FBNet

Class Project for 18663 - Implementation of FBNet (Hardware-Aware DNAS)

ProxylessNAS

[ICLR 2019] ProxylessNAS: Direct Neural Architecture Search on Target Task and Hardware.

PyTorch-Deep-Learning-Zero-to-All

Deep Learning Zero to All - Pytorch

quant_machine

슬기로운 퀀트투자 실습파일

raindrop-removal-CSED441-2019

rust_hello

SkyNet

solid

spooNN

FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)

yolov2_xilinx_fpga

A demo for accelerating YOLOv2 in xilinx's fpga pynq

zap

Predicting zero-valued activations with lightweight convolutional neural networks