Early experiments using SYCL single-source modern C++ on Xilinx FPGA, Ronan Keryell (Xilinx Research Labs, Dublin, Ireland) & Lin-Ya Yu (Xilinx Research Labs, Dublin, Ireland). IWOCL '18 Proceedings of the International Workshop on OpenCL. Oxford, United Kingdom — May 14 - 16, 2018.
Article: src/DHPCC-2018-triSYCL-FPGA-final.pdf
https://www.iwocl.org/iwocl-2018/dhpcc/
http://sycl.tech/distributed-heterogeneous-programming-in-c-cpp-dhpccpp18.html
https://easychair.org/cfp/DHPCC18
Submission: ttps://easychair.org/conferences/?conf=dhpcc18
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Review 1 Overall evaluation: 1: (weak accept) The paper gives a broad overview on the SYCL programming model and its implementation in the triSYCL system. It introduces the advantages of those for the heterogeneous architectures we see emerging today and even more so in the future. Presenting this overview to the attendees of the DHPCC workshop will add an interesting facet to its program. Review 2 Overall evaluation: 2: (accept) This paper presents the authors experiences and results using SYCL to target Xlinx FPGA devices. They show how using standard SYCL with some specific extensions they are able to write natural looking code that can efficiently execute on FPGA devices. The paper provides a clear motivation for the work, describing the growing heterogeneity in HPC resources, and also provides a thorough introduction to the SYCL programming model. The descriptions are augmented with clear code snippets which make the paper easy to follow. The authors introduce concepts to help express pipelining, dataflow and array partitioning and use these to write an array transfer benchmark, for which they present results. The results could be presented with some more detailed analysis, as some of the surprising points on the graph lack explanation. E.g. why does execution time increase for some of the tools and languages increase when switching to a newer SDK? This is an interesting paper that is a good choice for inclusion in DHPCC++, and should be an interesting presentation. Review 3 Overall evaluation: 2: (accept) This paper discusses an on-going open-source project called triSYCL used to experiment with the SYCL standard. This framework has been extended to target Xilinx SDx tool to compile SYCL programs to run on a CPU host connected to FPGA cards.
The authors instead of using #pragma or attributes or extensions prefer to have some pure C++ function based or class based extensions, compatible with CPU emulation and that aligns with SYCL DSeL philosophy.
Readability can be improved! Line 360, optimizations such as a bunch of reference paper numbers does not particularly help.
I didn’t quite follow the significance of using 2017.2 and 2017.4 with different clang and llvm versions, for figure 6 experiments. Axes should be labeled, always! It seems clang/llvm 3.9 using 2017.2 takes a longer time than 2017.4 . It would help to add more explanation if you are trying to recommend one version over the other for particular runs. The turquoise bar for single-source (SYCL) is lower than the rest but the red bar seems to be as tall as for 3.1 and 3.9 OpenCL d+p. Why so? Or group d+p and no opt bars together for say HLS C++ set. There should be a better way to represent Fig.6 and tell a story- you have tools, w/ and w/o optimizations, Xilinx SDx versions and Clang/LLVM versions.
I would have loved to see what the task graph looks like or some sort of representation of this task graph in a pen & paper sort of a way.
I like how you have concluded your paper! “With modern C++, there are less reasons to choose between “slow and convenient” and “fast and hard-to-use” programming models and we are seeing more an evolution from “fast and hard-to-use” towards a “fast and easy-to-use” paradigm”
I would like to see evaluations on real applications before I would conclude that triSYCL is competitive to other conventional programming tools and languages. More specifically an application evaluated against OpenCL and Verilog/VHDL and triSYCL. This will give us a taste of reality.
Having said that, FPGAs are very hard to program, so to that end, I like this triSYCL tool from Xilinx Research Labs. This effort is targeting on some of the real challenges with FPGAs. Thanks for including code snippets and thanks for making these code snippets available on GitHub
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