kbbuch

Kunal Buch's repositories

Verification of a 5 stage LC3 pipelined CPU with System Verilog and Mentor Graphics ModelSim

Language:SystemVerilog800

Verilog design of the 10x10 Tridiagonal Matrix Inversion hardware accelerator using synopsys design compiler.

Language:Verilog3 10

CUDA optimization of 2D Convolution

Language:Cuda100

Cache Hierarchy simulator

Language:C++010

Verification of Decode Stage using UVM

Language:SystemVerilog000