KANG Jian's repositories
FlooNoC
A Fast, Low-Overhead On-chip Network
common_ips
This is some common ips used in digital circuit design
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
DMT-for-VLC-FPGA
This is the project of VLC transmitter employing DMT with bit and energy allocation
DMT-for-VLC-MATLAB
Simulation of OFDM VLC with bit and energy allocation
Ethernet_test_Alinx2Aritix-7
This is the project modified from the AX516 Ethernet test demo transplant to Artix-7 developing board
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
verilog_everyday
the result of verilog everyday activity
verilog_everyday_prj
simulation project file and result
practicalAI
📚 A practical approach to learning and using machine learning.
python_experiment
for python and ml learning
VLC_OFDM_Simulation_original
This is original version.
video_trans_pro
This is the first version of video transmission project. 100Mbps Ethernet Port and UART serial port(4Mpbs)
video_trans_advanced
This is the second version of video transmission project using 1000Mbps Ethernet and GTP(500Mbps) as serial port.
WORK_PROCESS
This is the work summary of Jimmy
FIR_FILTER
THE COURSE PROJECT OF VLSI
vlsi_project
The template for VLSI project
Operating_system_on_ONetSwitch20
plant Linux system on ONetSwitch20 and make the system support the network switches
u-boot-xlnx
The official Xilinx u-boot repository
Digital-System-Design-and-Generation
Digital System Design and Generation - System Verilog Projects