jsleroy / riscv-arch-test

🔴 IMPORTANT DISCLAIMER 🔴

The current default branch [master] will be completely replaced with branch riscof-dev on 1st MAY 2022. This transition essentially migrates the current framework to the RISCOF framework. This provides a much richer and configurable environment for targets to test their compatibility. The current framework will be archived and NO LONGER SUPPORTED AFTER 1st MAY 2022. It is therefore recommended that ALL model/target owners migrate their targets to the riscof environment ASAP. More information on porting your target to RISCOF is available here: https://riscof.readthedocs.io/en/stable/

RISC-V Architecture Test SIG

This is a repository for the work of the RISC-V Foundation Architecture Test SIG. The repository owners are:

• Neel Gala (InCore Semiconductors)
• Marc Karasek (Inspire Semiconductors)

Details of the RISC-V Foundation, the work of its task groups, and how to become a member can be found at riscv.org.

For more details and documentation on the current testing framework see: doc/README.adoc

For more details on the test format spec see: spec/TestFormatSpec.adoc

For contributions and reporting issues please refer to CONTRIBUTION.md

Test Disclaimers

The following are the exhaustive list of disclaimers that can be used as waivers by target owners when reporting the status of pass/fail on the execution of the architectural suite on their respective targets.

1. The references uploaded for the following misaligned load/store tests will match targets which do not support misaligned load/stores in hardware. Targets with hardware misaligned support for load/stores will fail these tests.

   1. rv32i_m/privilege/src/misalign-[lb[u],lh[u],lw,sh,sb,sw]-01.S
   2. rv64i_m/privilege/src/misalign-[lb[u],lh[u],lw[u],ld,sb,sh,sw,sd]-01.S

2. The references uploaded for the following misaligned instruction tests will match targets which have compressed extension support enabled by default. Targets without the compressed extension support will fail the following tests:

   1. rv[32/64]i_m/privilege/src/misalign-b[ge[u],lt[u],eq,ne]-01.S
   2. rv[32/64]i_m/privilege/src/misalign2-jalr-01.S

3. The machine mode trap handler used in the privilege tests assumes one of the following conditions. Targets not satisfying any of the following conditions are bound to fail the entire rv32i_m/privilege and rv64i_m/privilege tests:

   1. The target must have implemented mtvec which is completely writable by the test in machine mode.
   2. The target has initialized mtvec, before entering the test (via RVMODEL_BOOT), to point to a memory location which has both read and write permissions.

Contribution process

Please refer to to CONTRIBUTION.md for guidelines on contributions.

Licensing

In general:

• code is licensed under one of the following:
  • the BSD 3-clause license (SPDX license identifier BSD-3-Clause);
  • the Apache License (SPDX license identifier Apache-2.0); while
• documentation is licensed under the Creative Commons Attribution 4.0 International license (SPDX license identifier CC-BY-4.0).

The files COPYING.BSD, COPYING.APACHE and COPYING.CC in the top level directory contain the complete text of these licenses.

Engineering practice

• Documentation uses the structured text format AsciiDoc. See doc/README.adoc for more details.

• Some directories use ChangeLog files to track changes in the code and documentation. Please honor these, keeping them up to date and including the ChangeLog entry in the git commit message.

• Please include a comment with the SPDX license identifier in all source files, for example:

// SPDX-License-Identifier: BSD-3-Clause

Quick Links:

• RISCOF [DOCS] [REPO]: This is the next version of the architectural test framework currently under development
• RISCV-ISAC [DOCS] [REPO] : This is an ISA level coverage extraction tool for RISC-V which used to generate the coverage statistics of the architectural tests.
• RISCV-CTG: [DOCS][REPO]: This is a RISC-V Architectural Test generator used to generate some of the tests already checked into this repository.
• Videos: This Global Forum 2020 video provides an introduction to the above mentioned tools
• riscvOVPsim: Imperas freeware RISC-V reference simulator for compliance testing
• riscvOVPsimPlus: Imperas enhanced freeware RISC-V reference simulator for test development and verification