This code came about following a series of blogs/threads on "All Programmable Planet".com A Xilinx-supported web-site about FPGA, but because of too much diversity (Altera referrals?) was shamelessly taken off the air without leaving an archive. What an arrogance! The moderator 'UBM' is to blame as well. Read their apologies over here: <allprogrammableplanet.com> which is redirected to UBM/EETimes where big promises are made, but none kept. The replacement section Programmable Logic has never reached the APP level. About 90% of the comments originate from a tea party where men of age (although some even younger then me) jibber-jabber about all things except FPGA. Quite the opposite of APP. There a few good articles now and then, mostly from guest bloggers.
Let's end this rant...
On the APP site several incarnations were discussed, like MCU, Picoblaze ..., but no real FPGA/HDL stuff. Out of curiosity I coded my own version in VHDL.
You will notice there is no test-bench, yet. Test-benches in VHDL are a chore, and in this case we would struggle a lot to represent the rectangular array, so I put that off. Now I had been looking at MyHDL and Python for quite some time and it occurred to me that writing a test-bench in Python would be alot more fun and eventually would lead to a graphical display, and that's what one expects from a Game of Life-machine?
Watch the MyHDL version coming up soon