Yu-Sheng Lin (johnjohnlin)

johnjohnlin

Geek Repo

Location:Taiwan

Github PK Tool:Github PK Tool


Organizations
mediaic

Yu-Sheng Lin's repositories

nicotb

A lightweight library to perform Python/Verilog co-simulation with Python3.3 coroutine + numpy. The name Nicotb cames from NatIve COroutine TestBench.

Language:PythonLicense:GPL-3.0Stargazers:21Issues:5Issues:1

UMI

This project implements the paper "Unrolled Memory Inner-Products: An Abstract GPU Operator for Efficient Vision-Related Computations" (ICCV 2017).

Language:C++License:GPL-3.0Stargazers:12Issues:3Issues:0

namedtuple

Implementation of super-fast C++-styled namedtuple, for compile-time reflection.

Language:C++License:NOASSERTIONStargazers:5Issues:2Issues:0

oreilly_cover

O'Reilly cover in LaTeX

Language:TeXStargazers:3Issues:2Issues:0
Language:TypeScriptStargazers:3Issues:2Issues:0

Linux-tips

錦囊妙計

License:GPL-3.0Stargazers:2Issues:0Issues:0

MyCourseProjects

as title...

Language:C++Stargazers:2Issues:2Issues:0

fb_musume

I will describe it later

Language:JavaScriptStargazers:1Issues:2Issues:3

johnjohnlin.github.io

Github IO repo

Stargazers:0Issues:1Issues:0
Language:ShellStargazers:0Issues:1Issues:0

cocotb

Coroutine Co-simulation Test Bench

Language:PythonLicense:NOASSERTIONStargazers:0Issues:1Issues:0

cppman

C++ 98/11/14 manual pages for Linux/MacOS

Language:PythonLicense:GPL-3.0Stargazers:0Issues:1Issues:0

FastBuild

Minecraft FastBuild Plugin

Language:JavaLicense:GPL-3.0Stargazers:0Issues:3Issues:0
Language:C++Stargazers:0Issues:3Issues:0

memhierbench

An approach for reproducing the AIDA64 benchmark using C++.

Language:C++Stargazers:0Issues:2Issues:0

native_verilator_gtkwave_lxt

Proof of Concepts: Supporting LXT2 file format (used by GTKWave) in Verilator.

Language:C++Stargazers:0Issues:1Issues:0

neosnippet-snippets

The standard snippets repository for neosnippet

Stargazers:0Issues:1Issues:0

ntuee_dclab_material

This repo is the lab materials for NTUEE DCLAB (http://dclab.ee.ntu.edu.tw).

Language:SystemVerilogStargazers:0Issues:2Issues:0

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

License:Apache-2.0Stargazers:0Issues:0Issues:0
Language:CLicense:GPL-3.0Stargazers:0Issues:0Issues:0

ramulator

A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf

Language:C++License:MITStargazers:0Issues:1Issues:0

sysbench

Scriptable database and system performance benchmark

Language:CLicense:GPL-2.0Stargazers:0Issues:1Issues:0

verilator

Verilator open-source SystemVerilog simulator and lint system

Language:C++License:LGPL-3.0Stargazers:0Issues:0Issues:0

verilator_fork

A fork of Verilator 3.9 http://git.veripool.org/git/verilator

Language:C++License:LGPL-3.0Stargazers:0Issues:1Issues:0
Language:C++Stargazers:0Issues:0Issues:0