Implement a bitonic sorting network on FPGA
Sometimes, it's necessary to implement a sorting module on FPGA. And those sorting algorithms which work well on CPU are not that suitable for FPGA. A usual method to sort a fixed amount of inputs is to use a sorting network. So, here, I implement a bitonic sorting network with verilog.
Just as its name implies, bitonic sorting network is a sorting network which could sort two groups of sorted data. And the two groups of sorted data, or inputs, should have opposite ascending features. To be more specific, please check out the introduction on wiki.
Briefly, the structure is as the figure below. It's from wiki as well.
