jihandong / openmips32

trivial CPU

openmips

my trivial CPU

• chap4: pipeline supports ORI;
• chap5: support and, or, xor, etc..., and their Data Hazard;
• chap6: add hilo_reg.v module, support mov, mfhi, mthi, etc..., and their Data Hazard;
• chap7: add arithmetic inst and mul, div inst;
• chap8:jump and branch inst, and Branch Hazard;
• chap9:load and store inst,