my trivial CPU
- chap4: pipeline supports
ORI
; - chap5: support
and, or, xor, etc...
, and their Data Hazard; - chap6: add
hilo_reg.v
module, supportmov, mfhi, mthi, etc...
, and their Data Hazard; - chap7: add
arithmetic
inst andmul
,div
inst; - chap8:
jump
andbranch
inst, and Branch Hazard; - chap9:
load
andstore
inst,