jialinlu

jialinlu

Geek Repo

Company:Fudan University

Location:Shanghai

Github PK Tool:Github PK Tool

jialinlu's repositories

Language:PythonLicense:BSD-3-ClauseStargazers:23Issues:1Issues:2
Language:PythonLicense:BSD-3-ClauseStargazers:11Issues:1Issues:0

skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

Language:PythonLicense:Apache-2.0Stargazers:1Issues:1Issues:0

adsbenchmark

Benchmark circuits for analog defect simulation including P2427 standard validation

Language:SystemVerilogLicense:MITStargazers:0Issues:0Issues:0
Language:C++License:BSD-3-ClauseStargazers:0Issues:1Issues:0

AMPSE

This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download IPs generated by AMPSE or parameterized IPs with neural network based parameter-metric regression models. Watch this repository and follow USCPOSH on GitHub for our further updates! USC POSH Group: https://github.com/USCPOSH

Language:PythonLicense:Apache-2.0Stargazers:0Issues:1Issues:0

BAG2_cds_ff_mpt

BAG2 workspace for fake PDK (cds_ff_mpt)

Language:PythonLicense:BSD-3-ClauseStargazers:0Issues:1Issues:0

boardgame2

Extension of OpenAI Gym that implements multiple two-player zero-sum 2-dimension board games

Language:PythonStargazers:0Issues:1Issues:0

CktGNN

Open Circuit Benchmark OCB and source code for CktGNN (https://openreview.net/forum?id=NE2911Kq1sp).

Language:PythonLicense:MITStargazers:0Issues:0Issues:0

D-VAE

D-VAE: A Variational Autoencoder for Directed Acyclic Graphs, NeurIPS 2019

Language:PythonLicense:MITStargazers:0Issues:0Issues:0

DAC-2020-Tutorial

Material for OpenROAD Tutorial at DAC 2020

Language:PythonLicense:BSD-3-ClauseStargazers:0Issues:1Issues:0

daily_fudan

一键平安复旦小脚本,自动化快速上报疫情

Stargazers:0Issues:0Issues:0

freepdk-45nm

ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

Language:VerilogStargazers:0Issues:1Issues:0

KDTree

Simple C++ KD-Tree implementation

License:BSD-3-ClauseStargazers:0Issues:0Issues:0

MAGICAL

Machine Generated Analog IC Layout

Language:C++License:BSD-3-ClauseStargazers:0Issues:1Issues:0

MAGICAL-CIRCUITS

Circuit release of the MAGICAL project

Language:SourcePawnLicense:BSD-3-ClauseStargazers:0Issues:1Issues:0

MatrixCircEvolutions

An evolutionary algorithm for automatic analog circuit topology synthesis.

Language:PythonStargazers:0Issues:1Issues:0

OpenFASOC

Fully Open Source FASOC generators built on top of OpenROAD

Language:MakefileLicense:Apache-2.0Stargazers:0Issues:1Issues:0

OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow

Language:VerilogLicense:NOASSERTIONStargazers:0Issues:1Issues:0
Language:PythonStargazers:0Issues:1Issues:0

PragmaticProgrammer

LeetCode and OJ Problems

License:MITStargazers:0Issues:0Issues:0
Language:TeXStargazers:0Issues:1Issues:0

RDF-2019

DATC RDF

Language:VerilogLicense:MITStargazers:0Issues:1Issues:0
Language:C++License:GPL-3.0Stargazers:0Issues:1Issues:0

rl-book

Source codes for the book "Reinforcement Learning: Theory and Python Implementation"

Stargazers:0Issues:0Issues:0

sdm_topo_dse

Automated High-Level Topology Synthesis Method for SDMs via Bi-level Bayesian Optimization

Language:PythonStargazers:0Issues:0Issues:0

TritonSizer

UCSD Sizer for leakage/dynamic power recovery, timing recovery

License:BSD-3-ClauseStargazers:0Issues:0Issues:0

UT-AnLay

Analog Placement Quality Prediction

License:BSD-3-ClauseStargazers:0Issues:0Issues:0

UW-IDEA_AnalogTestCases

Circuit Release for Analog Test Cases from UW IDEA project

License:Apache-2.0Stargazers:0Issues:1Issues:0