Jesse C. Lin's repositories
A2G
Analog layout generator
amaranth
A modern hardware definition language and toolchain based on Python
Analog-Mixed-Signal-Simulation-and-Modeling
This is my labs for the AMS simulation and modeling Training of Siemens EDA in Summer 2022, delivered by Dr. Hesham Omran.
ArxivPapers
Code behind Arxiv Papers
astran
ASTRAN - Automatic Synthesis of Transistor Networks
examples
Pre-built mlpack models
extension-summarize-translate-gemini
Chrome extension to summarize and translate web pages. Uses Gemini as the backend.
HDLGen-ChatGPT
HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project
hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
hwtLib
hardware library for hwt (= ipcore repo)
lcapy-gui
A graphical user interface for symbolic circuit analysis using Lcapy
gpt-researcher
GPT based autonomous agent that does online comprehensive research on any given topic
ml4dv
LLM4DV
oh
Verilog library for ASIC and FPGA designers
ollama
Get up and running with Llama 2, Mistral, and other large language models locally.
pygmid
A python3 gm/ID starter kit
RALF
Reinforcement learning assisted analog layout design flow.
SpinalDoc-RTD
The sources of the online SpinalHDL doc (Japanese Translation)
Standard-Cell-Characterization
Open Source tool to build liberty files and for Characterizing Standard Cells.
Synthetic-Test-Data-Generation-for-RAG
Synthetic Test Data Generation for RAG systems using RAGAS.
veriloggen
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
vpw-testbench
Verilator Python Wrapper and testbench framework
xls
XLS: Accelerated HW Synthesis