jerryw95

basic_verilog

Must-have verilog systemverilog modules

rad-flow

The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration devices (RADs). These devices incorporate conventional FPGA fabrics, several coarse-grained domain-specialized accelerator blocks, and high-performance networks-on-chip for system-level communication.

MVU

Neural Network accelerator powered by MVUs and RISC-V.

systemverilog

SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow

CUDA-Learn-Notes

🎉CUDA&C++ 笔记 / 大模型手撕CUDA / 技术博客，更新随缘: flash_attn、sgemm、sgemv、warp reduce、block reduce、dot product、elementwise、softmax、layernorm、rmsnorm、hist etc.

llm.c

LLM training in simple, raw C/CUDA

cuda-samples

Samples for CUDA Developers which demonstrates features in CUDA Toolkit

Linear-Algebra

tiny-gpu

A minimal GPU design in Verilog to learn how GPUs work from the ground up

Near-Maximum-Independent-Set

Near-linear time algorithm for computing near-maximum independent set

KaMIS

Maximum independent sets and vertex covers of large sparse graphs.

dgl

Python package built to ease deep learning on graph, on top of existing DL frameworks.

MetaVC

Repository for MetaVC -- A Meta Local Search Framework For Minimum Vertex Cover (MinVC)

MinimumVertexCover_DRL

Learning to solve Minimum Vertex Cover using Graph Convolutional Networks and RL

MNN

MNN is a blazing fast, lightweight deep learning framework, battle-tested by business-critical use cases in Alibaba

CUDA_Freshman

grok-1

Grok open release

pygcn

Graph Convolutional Networks in PyTorch

GCN_Partitioning

Graph Partitoning Using Graph Convolutional Networks

METIS

METIS - Serial Graph Partitioning and Fill-reducing Matrix Ordering

graph-partitioning-algorithms

Multi-way graph partitioning algorithms: FMS (Fiduccia-Mattheyses-Sanchis), PLM (Partitioning by Locked Moves), PFM (Partitioning by Free Moves)

Graph-Partitioning

The implementation is based on the Fiduccia-Mattheyses algorithm.

aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

oh

Verilog library for ASIC and FPGA designers

CNN-Accelerator-Implementation-based-on-Eyerissv2

CNN-Accelerator-VLSI

Convolutional accelerator kernel, target ASIC & FPGA

hello-algo

《Hello 算法》：动画图解、一键运行的数据结构与算法教程。支持 Python, Java, C++, C, C#, JS, Go, Swift, Rust, Ruby, Kotlin, TS, Dart 代码。简体版和繁体版同步更新，English version ongoing

GraphBLAS

SuiteSparse:GraphBLAS: graph algorithms in the language of linear algebra. For production: (default) STABLE branch. Code development: ask me for the right branch before submitting a PR. video intro: https://youtu.be/Tj5y6d7FegI .

suitesparse-metis-for-windows

CMake scripts for painless usage of SuiteSparse+METIS from Visual Studio and the rest of Windows/Linux/OSX IDEs supported by CMake

CUDALibrarySamples

CUDA Library Samples