jerrylioon's starred repositories
ISP-pipeline-hdrplus
Denoise,HDR,Isppipeline,Image-processing(图形处理),camera, Isp ,HDRplus
zynq_cam_isp_demo
基于verilog实现了ISP图像处理IP
awesome-ISP
A curated list of awesome ISP frameworks, papers, libraries, resources, and shiny things.
e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
riscv-tools
RISC-V Tools (ISA Simulator and Tests)
style-guides
lowRISC Style Guides
wavedrom.github.io
Digital timing diagram editor
wujian100_open
IC design and development should be faster,simpler and more reliable
Cores-VeeR-EH1
VeeR EH1 core
e203_hbirdv2
The Ultra-Low Power RISC-V Core
basic_verilog
Must-have verilog systemverilog modules
riscv-asm-manual
RISC-V Assembly Programmer's Manual
Zotero_introduction
A Short Chinese Introduction to Zotero
flops-counter.pytorch
Flops counter for convolutional networks in pytorch framework