jerrylioon

nerdtree

A tree explorer plugin for vim.

fzf.vim

fzf :heart: vim

openISP

Image Signal Processor

ISP-pipeline-hdrplus

Denoise,HDR,Isppipeline,Image-processing(图形处理),camera, Isp ,HDRplus

zynq_cam_isp_demo

基于verilog实现了ISP图像处理IP

awesome-ISP

A curated list of awesome ISP frameworks, papers, libraries, resources, and shiny things.

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

riscv-tools

RISC-V Tools (ISA Simulator and Tests)

style-guides

lowRISC Style Guides

wavedrom.github.io

Digital timing diagram editor

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

wujian100_open

IC design and development should be faster，simpler and more reliable

Cores-VeeR-EH1

VeeR EH1 core

e203_hbirdv2

The Ultra-Low Power RISC-V Core

openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

basic_verilog

Must-have verilog systemverilog modules

LF-Building-a-RISC-V-CPU-Core

riscv-asm-manual

RISC-V Assembly Programmer's Manual

SpinalHDL

Scala based HDL

Zotero_introduction

A Short Chinese Introduction to Zotero

torchstat

Model analyzer in PyTorch

flops-counter.pytorch

Flops counter for convolutional networks in pytorch framework