jeras

rp32

RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).

SystemC-UVM

UVM-SystemC Library

sockit_spi

SocKit SPI (3-wire, dual, quad) master

riscv_asm_sv

RISC-V assembler/dis-assembler written in SystemVerilog

SystemC-Verification

SystemC Verification Library (SCV)

vivado_simulator

Evaluation of the Xilinx Vivado simulator

ADAMS

all digital PLL

TCB

Tightly Coupled Bus, low complexity, high performance system bus.

cellular-automata-sage-toolkit

Automatically exported from code.google.com/p/cellular-automata-sage-toolkit

example-systemverilog

fpga_pio

An attempt to recreate the RP2040 PIO in an FPGA

HDL-CRC

CRC implementation in HDL languages (VHDL, SystemVerilog)

jtag_pulp

learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

Modern-Computer-Architecture-and-Organization-Second-Edition

Modern Computer Architecture and Organization – Second Edition, Published by Packt

openlane2

The next generation of OpenLane, rewritten from scratch with a modular architecture

PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

riscof

riscv-isa-manual

RISC-V Instruction Set Manual

riscv-isa-sim

Spike, a RISC-V ISA Simulator

sockit-stream

HDL streaming protocol library

SPH0641LU

The Converter board of Kicad Data for SPH0641LU

sv_fixed_point

SystemVerilog fixed point library

synthesis-optimizations

Observing and optimizing synthesis of common bit manipulation operations for FPGA and ASIC

SystemC

SystemC HDL library for C++

UHDM-integration-tests

UHDM-tests

Test for UHDM SystemVerilog plugin for yosys.

ultrasound_tof

Ultrasonic TOF (Time of Flight) measurement or distance measurement

UVVM

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

verilator

Verilator open-source SystemVerilog simulator and lint system