jdzhu19

RTLRewriter-Bench

antlr4

ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.

chipgptft

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)

FFT-cordic-HDL

FFT implementation using CORDIC algorithm written in Verilog.

32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

mpeg2fpga

An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.

firfilter

Verilog finite impulse response filter

polyphase_filter_prj

哈工大软件无线电课设：多相滤波器的原理、实现及其应用，从采样率变换、多相滤波器结构到信道化收发机应用都有matlab介绍和FPGA仿真结果，含答辩PPT、学习笔记和个人总结。

oss-cad-suite-build

Multi-platform nightly builds of open source digital design and verification tools

yosys

Yosys Open SYnthesis Suite

FlowTune

abc_py

Simple Python interface for ABC

RTL-Coder

A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.

RTLLM

An open-source benchmark for generating design RTL with natural language

VerilogProtoToken

VGen

networkx

Network Analysis in Python

mcgarnagle

Experimental garbled circuit optimizer

slang

SystemVerilog compiler and language services

egg

egg is a flexible, high-performance e-graph library

ruler

Rewrite Rule Inference Using Equality Saturation

verilog-eval

Verilog evaluation benchmark for large language model

Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

LLM4HWDesign_Starting_Toolkit

LLM4HWDesign Starting Toolkit

portfolio-v2

My Web Developer's portfolio

portfolio-ideas

A curation of awesome portfolio website ideas for developers and designers to draw inspiration from. Raise a pull request to add more. 💜

responsive-portfolio-website-Alexa

Responsive Portfolio Website Using HTML, CSS & JavaScript

masterPortfolio

🔥 The Complete Customizable Software Developer Portfolio Template which lets you showcase your work and provides each and every detail about you as Software Developer.

developer-portfolios

A list of developer portfolios for your inspiration