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jdcasanasr / lagarto_v

An In-Order Implementation of the RISC-V Vector ISA based on the Lagarto Hun Processor

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Lagarto-V

An In-Order Implementation of the RISC-V Vector ISA based on the Lagarto Hun Processor

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An In-Order Implementation of the RISC-V Vector ISA based on the Lagarto Hun Processor

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Language:Verilog 54.5%Language:SystemVerilog 39.5%Language:Stata 6.0%Language:Assembly 0.1%