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jasonabele / ettus-fpga

GitHub mirror of Ettus USRP FPGA development

Home Page:http://ettus-apps.sourcerepo.com/redmine/ettus/projects/fpga

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GitHub mirror of Ettus USRP FPGA development

http://ettus-apps.sourcerepo.com/redmine/ettus/projects/fpga

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Language:Verilog 89.4%Language:VHDL 8.1%Language:Tcl 1.0%Language:Python 0.7%Language:C 0.7%Language:Shell 0.1%Language:Perl 0.0%