Dr. med. Jan Schiefer's repositories
General-Slow-DDR3-Interface
A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
aisler-support
AISLER support files
esp-wifi
A WiFi, Bluetooth and ESP-NOW driver for use with Espressif chips and bare-metal Rust
fomu-workshop
Support files for participating in a Fomu workshop
fpga-tidbits
Chisel components for FPGA projects
learn-fpga
Learning FPGA, yosys, nextpnr, and RISC-V
litex-rusty
Running Rust on a custom Ltex RiscV SOC
litex-rusty-app
Running Rust with a HAL on a custom Litex SOC
lolra
Transmit LoRa Frames Without a Radio
no2bootloader
USB DFU bootloader gateware / firmware for FPGAs
picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
SDRAM_Verilog
Verilog HDL implementation of SDRAM controller and SDRAM model
SpinalHDL
Scala based HDL
SpinalHDLIntegerDivider
An integer division module for FPGAs written in SpinalHDL..
SpinalTemplateSbt
A basic SpinalHDL project
SpinalWorkshop
Labs to learn SpinalHDL
std-training
Embedded Rust on Espressif training material.
T-FPGA
The circuit board is an integrated ESP32S3 and FPGA (GW1NSR-LV4CQN48PC6/I5) control chip. With the power management AXP2101 can be used to switch the voltage of different BANK areas.
tangnano9k-series-examples
Examples for the Lushay Labs tang nano 9k series
TangPrimer-20K-example
TangPrimer-20K-example project
TangPrimer-25K-example
TangPrimer-25K-example project
tock
A secure embedded operating system for microcontrollers
tt05-verilog-demo
Verilog Demo, updated for Tiny Tapeout 05
XPowersLib
Arduino,CircuitPython,Micropython, esp-idf library for x-powers power management series