Dr. med. Jan Schiefer (janschiefer)

janschiefer

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Location:Germany

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Dr. med. Jan Schiefer's repositories

General-Slow-DDR3-Interface

A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.

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aisler-support

AISLER support files

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esp-wifi

A WiFi, Bluetooth and ESP-NOW driver for use with Espressif chips and bare-metal Rust

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fomu-workshop

Support files for participating in a Fomu workshop

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fpga-tidbits

Chisel components for FPGA projects

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learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

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linux-on-litex-vexriscv

Linux on LiteX-VexRiscv

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litex-rusty

Running Rust on a custom Ltex RiscV SOC

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litex-rusty-app

Running Rust with a HAL on a custom Litex SOC

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lolra

Transmit LoRa Frames Without a Radio

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no2bootloader

USB DFU bootloader gateware / firmware for FPGAs

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picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

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SDRAM_Verilog

Verilog HDL implementation of SDRAM controller and SDRAM model

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SpinalHDL

Scala based HDL

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SpinalHDLIntegerDivider

An integer division module for FPGAs written in SpinalHDL..

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SpinalTemplateSbt

A basic SpinalHDL project

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SpinalWorkshop

Labs to learn SpinalHDL

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std-training

Embedded Rust on Espressif training material.

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T-FPGA

The circuit board is an integrated ESP32S3 and FPGA (GW1NSR-LV4CQN48PC6/I5) control chip. With the power management AXP2101 can be used to switch the voltage of different BANK areas.

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tangnano9k-series-examples

Examples for the Lushay Labs tang nano 9k series

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TangPrimer-20K-example

TangPrimer-20K-example project

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TangPrimer-25K-example

TangPrimer-25K-example project

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tock

A secure embedded operating system for microcontrollers

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tt05-verilog-demo

Verilog Demo, updated for Tiny Tapeout 05

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XPowersLib

Arduino,CircuitPython,Micropython, esp-idf library for x-powers power management series

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