Spartan 6

[Martin van der Werff]

Hi Jamie, this is a very interesting project you have here. I’m thinking of porting the rtl to small xilinx spartan-6 based devices (lx9 and/or lx16) . I was wondering how altera/intel specific your code is and how you assess the amount of work it would take. Are there any specific requirements on the fpga like internal sram, fifos and such?

[Jamie Iles]

There's really not that much vendor specific code - only the PLL, block RAMs and virtual JTAG which have fairly standard interfaces so I wouldn't imagine that it should be too much work on top of modifying the build system to work with the Xilinx toolchain, but I don't have any experience with the Xilinx flow.

[Martin van der Werff]

Showstopper probably will be the SystemVerilog. As it turns out the Xilinx toolchain for the 'old' devices does not support it, it does only do VHDL and 'plain' Verilog.