j4ger / cyclops

A verilog design of a simple VGA graphics card.

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Cyclops

Experimental multi-core 2D rasterizer array implementation in SystemVerilog.

Dependencies

  • Verilator
  • NVBoard (included in repo)
  • SDL2 lib
  • rust stable (for buffergen)

Build & Run

NVBoard=./nvboard make run

buffergen

A simple rust program for generating ram initialization file compatible with this project from images of any aspect ratio/resolution.

cd buffergen
cargo run -- -i <path-to-input-image> -o <path-to-output-image>

About

A verilog design of a simple VGA graphics card.

License:Apache License 2.0


Languages

Language:SystemVerilog 82.1%Language:Rust 7.1%Language:Makefile 5.8%Language:C++ 5.0%