shi's repositories
FusionAccel
RTL-level Convolutional Network Accelerator Implementation on Xilinx Spartan 6. Evaluation for scalability.
ZCU104-ChaiDNN
Out-of-the-box CHaiDNN implementation on Zynq ZCU104
verilog-fx3slvfifo
Control Cypress FX3 Slave FIFO with FPGA
verilog-dvp
verilog dvp transceivers, TX implemented on Arty A7-35T, RX implemented on Basys 3 with direct VGA output
verilog-rmii
Example platform for Xilinx MII_to_RMII IP on Arty A7-35T, including ethernet RX and TX
verilog-mii
Example platform for Xilinx AXI_EthernetLite (MII) on Arty A7-35T, including active TX driven by AXI Traffic Generator and dummy RX
rmii_kintex
RTL RMII Ethernet Implementation on Kintex 7
checkespeare
Literature Collection in F-1 Check University
verilog-ethernet
Verilog Ethernet components for FPGA implementation
Iapetos
An imitation of the Binding of Isaac with cocos2dx
CMSIS
Cortex Microcontroller Software Interface Standard
Erriapo
Getting rid of the laggy epub readers on Windows
SqueezeNet
SqueezeNet: AlexNet-level accuracy with 50x fewer parameters
Tracing-Android
A social and game app based on map service on Android
vivado-build-system
Vivado build system
Wonton
Wonton