Yes, it's been done to death... another stack machine optimized for Forth, and oh look, it's written in VHDL, how boring. Well, I wanted to get my hands dirty anyways :)
YAFC (rhymes with KAFKA) is a soft-core, FPGA-targeted 16-bit dual-stack processor. It is designed to run Forth code natively.
It currently supports all of what I call the "primitive" Forth operations.
- Soft-core processor (targeted at small Xilinx and Altera's smaller offerings).
- Written entirely in portable VHDL'93 (prefer inference to instantiation of device primitives, to encourage reuse). The only caveat here is the PLL. This obviously calls for a vendor-specific IP core, depending on what brand of FPGA you use.
- Support single-cycle execution of as many Forth "primitives" as possible (I believe more than the full subset necessary to implement the interpreter in software is implemented).
- Target 100MHz+ clock speed on a Xilinx Spartan-6 (Papilio Pro w/ LogicStart MegaWing - XC6SLX9).
- Take up less than 20% of slices on target device. (Currently it occupies 13% of the device's slices, and 25% of BRAM). It wouldn't be difficult to modify it to use less RAM; you would basically throw away some of the top instruction bits. I consider the goal met.
- Write a bootloader for it.
Well, I think I pretty much met my goals for this one. It's definitely got areas it could be improved. I was sort of lazy with adding functionality, only adding it when it was needed, which is why opcode selection is a little sloppy.
- 100 MHz 16-bit dual stack processor.
- Supports a generous subset of Forth primitives.
- 32-word deep data stack, 32-word deep return stack
- Supports single-cycle execution of nearly all opcodes (exceptions are jumps, branches, calling a word, or returning from a word). The overhead of calling a word (subroutine) is only 2 extra cycles, and with a 32 word deep return stack, highly factored code is encouraged.
- Serial (RS-232) bootloader, is the default program loaded into the onboard SRAM. There is an accompanying Python script which can send an Xilinx-style memory initialization file over your computer's UART to the running YAFC core, and then it will run that program until it is reset or turned off (several examples included).
- An assembler, written in Python. Note that programs are written as Python programs, and should be bootloaded into the core, after assembly. Also note that this file is a giant hack; in my defense, it was just something to get me going ASAP when I was ready to run programs in the core.
- 8K of Program / Memory space, and 8K of I/O space.
- UART and GPIO are the only (admittedly very simple) peripherals implemented as of yet.
Copyright (c) 2014, Tim Wawrzynczak. All rights reserved.
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