indieorganic's repositories
hdlgenerator
Generate VHDL/Verilog code from code with an easier to write, more compact syntax.
Language:CGPL-3.0000
v2sc
tool that converts VHDL or Verilog to Systemc (based on https://code.google.com/p/v2sc/)
Language:Java000
verilog-axis
Verilog AXI stream components
Language:PythonMIT000
verilog-ethernet
Verilog Ethernet components
Language:VerilogMIT000