imhcyx

Yuxiao Chen's repositories

nscscc-mips-cpu

Language:Verilog3 20

light-midi-parser

A very simple MIDI file parser.

Language:CMIT2 20

ast-interpreter

Advanced Compiling Techniques Assignment 1

Language:C++1 30

rocket-chip

Rocket Chip Generator

Language:ScalaNOASSERTION1 10

rt-lookup

routing table lookup algorithms

Language:C1 20

.vimrc

Backup of my .vimrc file

Language:Vim Script020

auto-inc-counter

Language:Verilog020

axi.vh

Verilog header for easier AXI interface declaration & connection

Language:SystemVerilogMIT010

axi_id_killer

AXI ID signal remover

Language:Verilog010

baremetal

Language:C020

bot

Language:Python020

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Language:CBSD-3-Clause000

comparch-mips-cpu

Language:Verilog020

compiler-lab

Backup of my compiler lab course project

Language:C++NOASSERTION010

cosim_bfm_library

HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI

Language:CNOASSERTION000

hw-dev-tools

Some tools useful for hardware development

Language:PythonMIT020

llvm-assignment2

Advanced Compiling Techniques Assignment 2

Language:LLVM020

llvm-assignment3

Advanced Compiling Techniques Assignment 3

Language:LLVM020

nine-calc

Language:C000

npgen

Number Proof Generator

Language:Ruby020

nscscc-func-r1

Language:Assembly010

nscscc-linux

Language:CNOASSERTION020

nscscc-pmon

Language:CNOASSERTION030

NutShell

RISC-V SoC designed by students in UCAS

Language:ScalaNOASSERTION010

os

os project source code version control

Language:C000

sniffer

Language:C++020

svg2pdf

Language:Batchfile010

ucas-covid19

ucas疫情防控每日填报助手

Language:Python010

WidthAdapter

Language:Verilog020

yosys

Yosys Open SYnthesis Suite

Language:C++ISC000