iceshy's repositories
iob-soc
RISC-V System on Chip Template
serv
SERV - The SErial RISC-V CPU
PulseRain_RISCV_MCU
PulseRain RISC-V MCU
riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
PulseRain_rtl_lib
PulseRain rtl library
FRV2100
PulseRain FRV2100 RISC-V Core
cores
Various HDL (Verilog) IP Cores
yosys
Yosys Open SYnthesis Suite
ibex
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
opentitan
OpenTitan: Open source silicon root of trust
openocd
Spen's Official OpenOCD Read-Only Mirror (no pull requests)
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
rocket-chip
Rocket Chip Generator
edalize
An abstraction library for interfacing EDA tools
common_cells
Common SV components
ariane
Ariane is a 6-stage RISC-V CPU capable of booting Linux
pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
axi
AXI4 and AXI4-Lite synthesizable modules and verification infrastructure
Cores-SweRV
SweRV EH1 core
TimEx
Netlist-to-Verilog extraction for SFQ circuits
hackdac_2018_beta
The SoC used for the beta phase of Hack@DAC 2018.
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
core_spiflash
SPI-Flash XIP Interface (Verilog)
riscv
RISC-V CPU Core (RV32IM)
apb
APB Logic
biriscv
32-bit Superscalar RISC-V CPU
senior_design_puf
Repository to store all design and testbench files for Senior Design
sha256
Hardware implementation of the SHA-256 cryptographic hash function
ReGDS-Logic-Gate-Extraction
A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the standard cell library.