iamgzi's repositories
5g-nr-pusch
MATLAB implementation of a transmitter and receiver chain of the 5G NR Physical Uplink Shared Channel (PUSCH) defined by 3GPP rel 15.
802.11ax
802.11芯片开发/验证资料
aws-fpga-app-notes
Application notes for the F1 EC2 Instance
btbd
bluetooth baseband
cloudimg
tuchuang
corundum
Open source, high performance, FPGA-based NIC
DeepLearning-500-questions
深度学习500问，以问答形式对常用的概率知识、线性代数、机器学习、深度学习、计算机视觉等热点问题进行阐述，以帮助自己及有需要的读者。 全书分为17个章节，20多万字。由于水平有限，书中不妥之处恳请广大读者批评指正。 未完待续............ 如有意合作，联系scutjy2015@163.com 版权所有，违权必究 Tan 2018.06
digital-fm-stereo-modulator
All-digital FM Stereo Modulator described in Verilog.
Digital-Hardware-Modelling
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
DSP-RTL-Lib
RTL Verilog library for various DSP modules
FPGA
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
fpga-partial-reconfig
Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
free-programming-books-zh_CN
:books: 免费的计算机编程类中文书籍，欢迎投稿
hdl
HDL libraries and projects
HLx_Examples
Open Source HLx Examples
hw
RTL, Cmodel, and testbench for NVDLA
ofdm_ieee80211a
OFDM baseband processing systerm based on IEEE 802.11a
openwifi
open-source Wi-Fi baseband chip/FPGA design
openwifi-hw
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
pp4fpgas
Parallel Programming for FPGAs -- An open-source high-level synthesis book
pp4fpgas-cn
中文版 Parallel Programming for FPGAs
SatCommSystem-QPSK-OFDM-LSEstimation-TransionosphericChannel
MATLAB Imitation Modeling for the BER of the Satellite Communication System using QPSK and OFDM Modulation with LS Channel Estimation based on Pilot Signals in the Transionospheric Communication Channel with Rician Fading, Multipath, Frequency Selectivity and Limited Coherence Bandwidth
verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
verilog-axi
Verilog AXI components for FPGA implementation
verilog-axis
Verilog AXI stream components for FPGA implementation
verilog-ethernet
Verilog Ethernet components for FPGA implementation
verilog-lfsr
Fully parametrizable combinatorial parallel LFSR/CRC module
Viterbi-Decoder-in-Verilog
An efficient implementation of the Viterbi decoding algorithm in Verilog
Xilinx-OpenHW-Contest
Xilinx OpenHW Contest Source Code